unsigned short svs_master(unsigned short *bufin16, unsigned short *bufout16, int bufoutsize) {
    unsigned short bufinsize = 0;
    int remainingBytes;
    unsigned short dummy;
    
    *pPORTF_FER |= (PF14|PF13|PF12|PF11|PF10);  // SLCK, MISO, MOSI perhipheral
    *pPORT_MUX |= PJSE;  // Enable PJ10 (SSEL2/3) PORT_MUX PJSE=1 
    *pSPI_BAUD = 4;
    *pSPI_FLG = FLS3;    // set FLS3 (FLG3 not required with CHPA=0
    *pSPI_CTL = SPE|MSTR|CPOL|SIZE|EMISO|0x00;  // we use CPHA=0 hardware control
    SSYNC;

  
    *pSPI_TDBR = bufoutsize & 0xffff;
    dummy = *pSPI_RDBR;  // slave will not have written yet
    SSYNC;
    while((*pSPI_STAT&SPIF) ==0 ); // ensure spi tranfer complete 
    while((*pSPI_STAT&TXS) >0 );  // ensure tx buffer empty
    while((*pSPI_STAT&RXS) ==0 ); // ensure rx buffer full
    *pSPI_TDBR = *bufout16++;
    SSYNC;
    bufinsize = *pSPI_RDBR;
    SSYNC;

    remainingBytes = max(bufinsize,bufoutsize);

    while(remainingBytes--) {        
        while((*pSPI_STAT&SPIF) == 0 ); // ensure spi tranfer complete 
        while((*pSPI_STAT&TXS) > 0 );  // ensure tx buffer empty
        while((*pSPI_STAT&RXS) ==0 ); // ensure rx buffer full
        *pSPI_TDBR = *bufout16++;
        SSYNC;
        *bufin16++ = *pSPI_RDBR; // read the dummy value from slave processor
        SSYNC;
    }
    *pSPI_CTL = 0x400;
    *pSPI_FLG = 0x0;
    *pSPI_BAUD = 0x0;
    SSYNC;
    return bufinsize;
}

unsigned short svs_slave(unsigned short *bufin16, unsigned short *bufout16, int bufoutsize) {
    unsigned short bufinsize = 0;
    int remainingBytes;

    *pPORTF_FER    |= (PF14|PF13|PF12|PF11|PF10);    // SPISS select PF14 input as slave,
                        // MOSI PF11 enabled (note shouldn't need PF10 as that's the flash memory)
    *pPORT_MUX    |= PJSE;     // Enable PJ10 SSEL2 & 3 PORT_MUX PJSE=1  not required as we're slave..
    *pSPI_BAUD    = 4;
    *pSPI_CTL     = SPE|CPOL|SIZE|EMISO|0x00; // tc on read
    SSYNC;

    *pSPI_TDBR = bufoutsize;
    SSYNC;
    bufinsize = *pSPI_RDBR;
    SSYNC;
    while( (remainingBytes>0) && ((*pSPI_STAT&TXS) > 0)  ); // ensure tx buffer empty
    while( (*pSPI_STAT&SPIF) == 0 ); // ensure spif transfer complete
    while( (*pSPI_STAT&RXS) == 0  ); // ensure rx buffer full
    *pSPI_TDBR = *bufout16++; 
    SSYNC;
    bufinsize = *pSPI_RDBR; // read full 16 bits in one
    while( ((*pSPI_STAT&TXS) > 0)  ); // ensure tx buffer empty

    remainingBytes = max(bufinsize,bufoutsize);
        
    while(remainingBytes--) {
        while( (*pSPI_STAT&SPIF) == 0 ); // ensure spif transfer complete
        while( (*pSPI_STAT&RXS) == 0  ); // ensure rx buffer full
        *pSPI_TDBR = *bufout16++; 
        SSYNC;
        *bufin16++ = *pSPI_RDBR; // read full 16 bits in one
        while( (remainingBytes>=0) && ((*pSPI_STAT&TXS) > 0)  ); // ensure tx buffer empty
    };

    *pSPI_CTL = 0x400;
    *pSPI_FLG = 0x0;
    *pSPI_BAUD = 0x0;
    SSYNC;
    return bufinsize;
}