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Clock divider for UART0 (Read 670 times)
tuetulip
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Posts: 17
Clock divider for UART0
02/26/10 at 3:09am
 
We want to remove the matchport from the SVS and use our own serial interface to communicate with the Blackfins. We successfully coupled the devices at 2.5Mbitps and 3Mbitps. We want to go up to 6Mbitps and this seems possibele, but we have trouble setting the clock divider in firmware. When we put 6M as baudrate(actually 6082450) in config.h, we measured 5Mbitps with oscilloscope. Then we tried directly setting the divider to 5 in uart.c, to get 6M, but instead we got ~7.1M!
This does not seem really consistent with
          MASTER_CLK x PLL
rate=--------------------------
           16 x Divisor
scheme.
 
Is there a guide to set the baud rate/divisor to achieve custom rates. Our serial interface can handle up to 12Mbitps.
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admin
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Posts: 3676
Re: Clock divider for UART0
Reply #1 - 02/26/10 at 7:24am
 
The available UART speeds depend on 4 factors:
 
1.  main crystal speed, which is 22.118MHz
2.  VCO_MULTIPLIER, currently set to 22
3.  SCLK_DIVIDER, currently set to 4
4.  UART0_DIVIDER
 
The core CPU speed equals crystal * VCO_MULTIPLIER = 486.6MHz.  To set a baud rate, this number is divided by 4, which gives you the memory bus speed (121.65MHz), and then divided by 16, which gives you the maximum UART speed (7.6MHz).  All possible UART speeds are then derived from this maximum.  If the UART0_DIVIDER is set to 1, your UART speed is 7.6Mbps.  Set to 2, it's 3.8Mbps.  Set to 3, it's 2.53Mbps, etc.
 
You could try other combinations of VCO_MULTIPLIER and SCLK_DIVIDER to achieve other UART speed settings, but you need to be careful, as I don't know whether you will hit any issues if the core CPU speed goes beyond 500MHz or the memory bus speed goes beyond the current 121MHz setting.
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